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153
XMEGA A [MANUAL]
8077I–AVR–11/2012
14.3
Block Diagram
Figure 14-2 on page 153 shows a detailed block diagram of the timer/counter without the extensions.
Figure 14-2. Timer/counter block diagram.
The counter register (CNT), period registers with buffer (PER and PERBUF), and compare and capture registers with
buffers (CCx and CCxBUF) are 16-bit registers. All buffer register have a buffer valid (BV) flag that indicates when the
buffer contains a new value.
During normal operation, the counter value is continuously compared to zero and the period (PER) value to determine
whether the counter has reached TOP or BOTTOM.
The counter value is also compared to the CCx registers. These comparisons can be used to generate interrupt
requests, request DMA transactions or generate events for the event system. The waveform generator modes use these
comparisons to set the waveform period or pulse width.
A prescaled peripheral clock and events from the event system can be used to control the counter. The event system is
also used as a source to the input capture. Combined with the quadrature decoding functionality in the event system
(QDEC), the timer/counter can be used for quadrature decoding.
14.4
Clock and Event Sources
The timer/counter can be clocked from the peripheral clock (clkPER) or the event system, and Figure 14-3 shows the
clock and event selection.
Base Counter
Compare/Capture
(Unit x = {A,B,C,D})
Counter
=
CCx
CCBUFx
Waveform
Generation
BV
=
PERBUF
PER
CNT
BV
= 0
"count"
"clear"
"direction"
"load"
Control Logic
CTRLD
CTRLA
OVF/UNF
(INT/DMA Req.)
ERRIF
(INT Req.)
TOP
"match"
CCxIF
(INT/DMA
Req.)
Control Logic
Clock Select
"e
v"
UP
DA
TE
BOTTOM
OCx Out
Event
Select
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